march 2008 rev 3 1/8 AN440 application note qii and qiii triac triggering with positive power supply introduction new triacs with high commutation and dv/dt performances are now available on the market. generally these triacs can be triggered only in the first three quadrants (case of snubberless?, logic level and snubberless high temperature triacs) as shown in figure 1 . this paper describes a trigger circuit supplying a negative gate current for quadrants ii and iii implemented in a system using a positive power supply. without a new design, just by adding a capacitor and a diode, new series triacs can replace conventional triacs. figure 1. the quadrants of snubberless, logic-level, and snubberless high temperature triacs tm: snubberless is a trademark of stmicroelectronics + + -- +- 1 st 2 nd 3 rd 4 th not triggerable i t i g + + -- +- 1 st 2 nd 3 rd 4 th not triggerable i t i g a 1 i g i t a 2 a 1 i g i t a 2 www.st.com
principle of proposed gate circuit AN440 2/8 1 principle of proposed gate circuit to drive the triac in the 2nd and 3rd quadrants, a discharge capacitor is used as shown in figure 2 . figure 2. basic diagram of the triggering circuit when the transistor tr is switched off, capacitor c is charged through resistance r2 and diode d. the diode is used to avoid a capacitor charging current through the triac gate. a schottky diode could be used to keep the voltage drop level below the gate non trigger voltage (v gd ). when the triac is triggered, tr transistor is switched on, c is discharged through r1 and tr and a negative current flows through the triac gate. we have to consider different parameters to define all the components: the triac gate triggering current (i gt ). the time duration of the gate current pulse. the triac latching current (i l ) especially for low rms current loads. + vcc line i/o mcu gnd load d r1 c r2 r3 triac tr + vcc gnd + vcc i/o mcu gnd load d r1 c r2 r3 triac tr + vcc gnd
AN440 gate current pulse width setting 3/8 2 gate current pulse width setting the triac latching current (i l ) is the minimum value of the main current which allows the component to remain in the conducting state after the gate current i g has been removed. that is to say the gate current has to be higher than i gt until the main current reaches the latching current. example: for most of cw snubberless triacs (refer to datasheet for further information): q1 ? q3: i l max = 50 ma q2: i l max = 60 ma example: for most bw snubberless triacs: q1 ? q3: i l max = 70 ma q2: i l max = 80 ma figure 3. gate control principle i a1 i g i lmax i gm t t 2 i gm t 1 t 1 i a1 i g i lmax i gm t t 2 i gm t 1 t 1
gate current pulse width setting AN440 4/8 t 1 calculation the triac gate has to be supplied to reach an anode current higher than the latching current. furthermore, a minimum gate current pulse width of 20 s has to be ensured. the minimum t 1 level is then given by the following equation: where = 2. .f and f is mains frequency. i rms : minimum rms current of the load (depending on line and load variations). figure 4 shows the minimum time versus i rms load current for a 50hz application. figure 4. t 1 time versus i rms for different load currents (worst case: ilq2) note: curve given for v ce = 1 v and v gk = 1.3 v i gt is the maximum gate trigger current specified in the data sheet. to ensure a good safety margin and a good triggering we chose i gm = 2.i gt . the gate resistor can be defined by the following equation: with typically v ce = 1 v and v gk = 1.3 v at i gm = 2.i gt capacitor c is then given by the following equation (where t 1 is given by figure 4 ): figure 5 gives the minimum capacitance versus supply voltage for different triacs series. to ensure that capacitor c will be charged for the nest half cycle, r 2 could be chosen with this equation (charging time constant < 1 ms): 20 s 2 i i asin 1 t rms max l 1 + ? ? ? ? ? ? ? ? 0 20 40 60 80 100 120 140 160 180 200 01234567891011121314151617181920 it(rms) (a) t1 (s) bw series cw series t1 (cw -> 60ma) t1 (bw -> 80ma) gm ce gk cc 1 i v v v r - - = () 2 ln r t c 1 1 c 0.001 r 2 <
AN440 gate current pulse width setting 5/8 figure 5. capacitance value versus supply voltage for different sensitivities 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 0 2 4 6 8 1012141618202224262830 vcc (v) c (f) bw series cw series c (cw -> 60ma) c (bw -> 80ma)
experimental results AN440 6/8 3 experimental results figure 6 gives a typical oscillogram within the following conditions: triac = bta08-600cw i rms = 2.12 a (load power: 500 w) line voltage: 230 v rms, 50 hz v cc = 5 v r 1 = 36 r 2 = 300 c = 3.3 f figure 6. triggering at zero current the component values are given in the following table for different application cases. table 1. component values for 3 different cases. triac: bta08-600cw (i gt = 35 ma) i rms = 2 a v cc = 5 v i rms = 5 a v cc = 5 v i rms = 5 a v cc = 10 v t 1min (s) 87.5 47 47 r 1max ( ) 39 39 110 c min (f) 3.3 1.76 0.62 r 2max ( ) 306 569 1622 gatecurrent div) gate current (50 ma/div) anode div) anode current (500 ma/div)
AN440 conclusion 7/8 4 conclusion in the case of controllers supplied by positive voltage this solution allows the replacement of conventional triacs used in the 1st and 4th quadrants by snubberless or logic level triacs which operate only in the first three quadrants. this solution only requires the addition of a capacitor and a diode to control each triac. with inductive loads (motor, transformer, etc...) a pulse train can be used because of the phase lag between current and voltage. in the case of logic or transistor failure, the capacitor c operates as an open circuit for dc current and avoids all triggering. this factor acts as a safety feature. but this trigger circuit can not be effectively used to drive small loads (like valves, fan etc...) because the latching current value is quite high compared to the load current. in this case a dc gate current is required. then the v cc point of the power supply should be connected to a 1 to sink the current directly from the gate with the control circuit. there is then no need of a supplementary capacitor and diode. this solution is then easier and cheaper. 5 revision history table 2. document revision history date revision changes may-1992 1 initial release. 23-apr-2004 2 style sheet update. no content change. 10-mar-2008 3 reformatted to current standards. full technical review
AN440 8/8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
|
